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FIR correction filter design and FPGA implementation for array mutual coupling error
YAO Zhicheng, WU Zhihui, YANG Jian, ZHANG Shengkui
Journal of Computer Applications    2019, 39 (8): 2374-2380.   DOI: 10.11772/j.issn.1001-9081.2019010131
Abstract474)      PDF (1001KB)(196)       Save
Focusing on the issue that the traditional Finite Impulse Response (FIR) filter slows down operation speed and consumes more resources under high-order conditions, a high-speed and high-order FIR filter design method based on piecewise convolution was proposed. Faster data processing was realized by the method of parallel processing in the frequency domain. Firstly, the design order M of the filter was determined and used as the reference sequence length, and the input digital signal was subjected to M period delay. Secondly, the original sequence and the delay sequence were respectively subjected to Fast Fourier Transform (FFT). Thirdly, the transformed sequences were respectively multiplied by the filter and then subjected to Inverse Fast Fourier Transform. Finally, the merging of the two way data was realized by the method of overlapping reservation. Theoretical analysis and simulation tests show that compared with the traditional distributed method based on Look Up Table (LUT), more than 30% of register resources were saved under the same order by the proposed method. On this basis, the measured data of the experimental platform were used for verification. Experimental results show that compared with the result of uncorrected mutual coupling error, the square root of the corrected amplitude mismatch is less than 1 dB and the root mean square of phase mismatch is less than 0.1 rad. Experimental data fully demonstrate the effectiveness of the method for mutual coupling error correction.
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